A prior art means for generating a noise-free signal which is locked in frequency and phase to the fundamental, a harmonic, or sub-harmonic of an input reference signal, which may be noisy, in the phase locked loop (PLL). Such circuits can function as frequency dividers if a subharmonic of the input frequency is chosen and can function as a frequency synthesizer if the circuitry is capable of selecting numerous different harmonics or subharmonics of the input frequency. These prior art PLLs have certain disadvantages, for example, they cannot function without the continuous application of the input frequency, and they are of an analog nature comprising a variable voltage controlled oscillator connected in a feedback loop which includes RC circuits. This circuitry with its inherent RC time constant means that the output frequency cannot instantly follow changes in the input frequency. Another disadvantage of these PLLs is that they are only capable of generating integral harmonics or sub-harmonics of the input frequency. One aspect of the present invention comprises a digital frequency divider or synthesizer which does not have these disadvantages.
One application of the present invention is to provide a digital tracking clock generator for an asynchronous multiplexer set, for example, the US Army's AN/GSC-24. This multiplexer set presently comprises equipment which is capable of providing asynchronous time division multiplexing and demultiplexing capabilities for a digital transmission network. The multiplexing function accepts up to 15 channels of source data at various different low rates and interleaves them into a single high speed data stream. After transmission, the demultiplexer separtes the high speed digital stream into 15 different user channels and applies each channel of data to its user data modem at the lower rate. To accommodate non-synchronous channels which may have somewhat different timing sources, this multiplexer set uses a technique known as "bit stuffing" and "bit de-stuffing". The composite high speed digital bit stream has a percentage of its time slots devoted to "overhead", which is used for synchronizing purposes as well as to compensate for changes in user data rates, which may vary over or under the multiplexer internal timing or clock. Thus if the number of bits per frame allotted to a given channel is not sufficient to transmit all of the bits arriving from that user during that frame, the extra bits are transmitted as stuffing bits during the overhead portion of the frame, and conversely if the input channel generates fewer bits than are allotted to it, a delete bit or bits are inserted in the overhead. The action taken on the demultiplexing side of the AN/GSC-24 to accommodate this overhead servicing is referred to as "bit destuffing", followed by "smoothing". Thus any extra overhead bits are inserted in the proper user's data stream and his clock rate automatically adjusted to take care of the extra bit. A delete bit in the overhead results in the deletion of a given bit and the smoothing of the user's clock rate to match that of the source input. The stuffing and delete operations result in the smoothing of the individual channel output data and clock rates or frequencies. The present design of this equipment includes an analog PLL of the type described above in each of the demultiplexer channel cards. These PLLs slew the channel output data/clock up or down in frequency in accordance with the stuff/de-stuff commands. This increase or decrease in the output of one bit time is accomplished over an extended number of clock periods. The smoothing buffer is presently designed so that this one bit correction must be accomplished in a time period of no more than approximately 2000 bit times. Such a slew rate exceeds the synchronization capabilities of certain user modems connected to this multiplexer set. These interoperability problems of the AN/GSC-24 with these user modems can be eliminated with the use of an asynchronous storage buffer controlled by a digital tracking clock generator, which is another aspect of the present invention. This digital tracking clock generator is a device that has as its input any timing signal and has an output which is the average of the input frequency. The advantage of such a circuit is that momentary changes in input, causes for example by stuffing and destuffing of the channel clock, may be averaged over a long period of time. This capability enables the tracking generator to recreate at the user's modem the channel clock that originated at the transmit modem and thus provides a high order of immunity to changes introduced by the multiplexer's stuffing and de-stuffing action.
The tracking clock generator uses the concepts of the digital frequency divider/synthesizer which is part of this invention.